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| 1/15 www.rohm.com 2010.05 - rev.a ? 2010 rohm co., ltd. all rights reserved. headphone amplifiers digital input class-d headphone amplifier BU7839GVW description most suitable for long duration reproduction of digital audio because digital audio data is taken as its input and low power consumption is realized.BU7839GVW has stereo audio da c and hp amp functions for digital audio playback. pop sound in ramp-up period is reduced due to built-in st art-up sound reduction circuit or transistor for mute. also, built-in digital volume which can control l-ch & r-ch separately. features 1) with stereo audio dac and hp amp functions 2) most suitable for long duration reproduction of digital audio because digital audio data is taken as its input and low power consumption is realized 3) pop sound in ramp-up period is reduced due to built-in st art-up sound reduction circuit or transistor for mute 4) built-in digital volume which can control l-ch & r-ch separately immediate switching and zero cross switching for reduc tion of clicking sound at the time of gain change gain change methods of soft switching can be selected with registers 5) sampling frequency compatible with 8khz-48khz 6) compatible with master slave with built-in pll 7) built-in soft mute function 8) compatible with full front and full back formats 9) compatible with 16, 18 & 24bit formats 10) compatible with fs=32khz,44.1k hz,48khz with de-emphasis function 11) 2wire cpu i/f (2 addresses selectable 33h, 36h) functions stereo audio dac + hpamp ? 2wire cpu i/f ? serial audio i//f ? interpolator ?? modulator ? level shifter ?pll no.10102eat03
technical note 2/15 www.rohm.com 2010.05 - rev.a ? 2010 rohm co., ltd. all rights reserved. BU7839GVW absolute maximum rating parameter symbol ratings unit analog power supply voltage avdd -0.3 4.5 v digital power supply voltage dvdd -0.3 2.1 v digital io power supply voltage dvddio -0.3 4.5 v terminal applied volt age 1 vin1 dvss-0.3 dvddio+0.3 v terminal applied voltage 2 *1 vin2 dvss-0.3 4.5 v allowance loss pd 520 *2 mw storage temperature range tstg -50 125 operation temperatur e range topr -30 85 * 1 sda,scl terminal * 2 when you use at above ta = 25 degree, 52mw are reduced concerning 1degree when you mount 114.6mm x 76.2mm x 1.6mm note:when you use under the conditions which exceed this value, there are times when the device is destroyed. in addition usual operation is not guaranteed. recommended operating range parameter symbol limits unit min typ max analog power supply voltage avdd 2.5 2.8 3.0 v digital io power supply voltage dvddio dvdd - 3.0 v digital power supply voltage dvdd 1.35 1.50 1.65 v technical note 3/15 www.rohm.com 2010.05 - rev.a ? 2010 rohm co., ltd. all rights reserved. BU7839GVW external size figure fig.1 external size figure (unit : mm) 1pin mark 0.08 s s ab s b a 0.08 4.00.1 4.00.1 0.08 0.9 max. 0.70.1 0.70.1 0.65 0.65 p=0.65x4 p=0.65x4 24- 0.330.05 lotno. 7839 technical note 4/15 www.rohm.com 2010.05 - rev.a ? 2010 rohm co., ltd. all rights reserved. BU7839GVW block diagram 2wire cpu i/f audio i/f interpolator ? modulator level shifter interpolator ? modulator level shifter register power on/off control mclk bclk lrclk sdi scl sda dvdd dvss adr test pll refclk dvddio dvssio 12mhz in vdd_r out_r vss_r vdd_l out_l vss_l pllcap pllvdd dvss mute_r mute_l 256fs nrst fig. 2 block diagram description of each block ? 2wire cpu i/f interface with cpu, 2-wire control write/read possible device address is 2-address selectable (33h,36h) with adr terminal ? register this lsi is controlled all by register write/read by 2wire cpu i/f ? audio i/f compatible with three modes of full front, full back and iis sampling frequency compatible with 8khz 48khz ? interpolator, ? modulator variable over sampling, order-variable ? modulator optimum value is selected internally and automatically ? level shifter level conversion in 3v series of analogue output built-in mute transistor for start-up sound reduction ? pll refclk terminal is taken as reference clock and 256fs is created it becomes the default setting when 12mhz is inputted to refclk please change each setting if any frequenc y other than 12mhz is inputted to refclk technical note 5/15 www.rohm.com 2010.05 - rev.a ? 2010 rohm co., ltd. all rights reserved. BU7839GVW terminal table no terminal name function classifi cation digital/ analog in/out rest middle / rear initial value note a1 mclk audio i/f master clock a d in/out in 256fs b3 bclk audio i/f bit clock b d in/out in 64fs a2 lrclk audio i/f lr clock b d in/out in fs c2 sdi audio i/f serial data e d in - c1 dvddio digital io vdd - d - - i/o power supply b4 scl 2wire cpu i/f serial clock c d in - a5 sda 2wire cpu i/f serial data d d in/out in b2 nrst reset e d in - l: reset a3 adr device address select e d in - l:33h or h:36h c3 test test pin e d in - please connect to the ground d1 dvdd digital core vdd - d - - digital power supply a4 dvss digital core vss - d - - digital ground ? b5 refclk reference clock h d in input 10m 20mhz d5 pllvdd pll vdd - a - - pll power supply c5 pllcap pll capacitor f a out hiz c4 dvss pll, digital vss - d - - pll, digital ground ? d4 vdd_r analog vdd - a - - rch power supply e4 out_r rch output g a out hiz e5 mute_r rch mute i a out hiz for starting sound decrease d3 vss_r analog vss - a - - rch ground e1 vdd_l analog vdd - a - - lch power supply e2 out_l lch output g a out hiz d2 mute_l lch mute i a out hiz for starting sound decrease e3 vss_l analog vss - a - - lch ground terminal equivalent circuit figure a dvddio dvssio lvs b dvddio dvssio lvs c dvssio lvs d dvssio lvs e dvddio dvssio lvs f pllvss pllvdd g vss_r vss_l vdd_r vdd_l vdd_r vdd_l vss_r vss_l h dvddio dvssio lvs i vdd_r vdd_l vss_r vss_l vss_r vss_l technical note 6/15 www.rohm.com 2010.05 - rev.a ? 2010 rohm co., ltd. all rights reserved. BU7839GVW application circuit chart 2.8v 0.1uf 220uf 2wire cpu i/f audio i/f interpolator ? modulator level shifter interpolator ? modulator level shifter register power on/off control mclk bclk lrclk sdi scl sda out_r vss_r out_l vss_l dvdd dvss adr test pll refclk pllcap dvddio nrst 0.068uf 12mhz in device address l: 33h h: 36h 1.5v dvdd2.8v pllvdd dvss mute_r mute_l dsp cpu 256fs 100uh 0.1uf 220uf 16 100uh l: reset vdd_r 2.8v vdd_l 2.8v 16 fig.3 application circuit chart measurement circuit chart 2.8v 0.1uf 220uf 2wire cpu i/f audio i/f interpolator ? modulator level shifter interpolator ? modulator level shifter register power on/off control mclk bclk lrclk sdi scl sda out_r vss_r out_l vss_l dvdd dvss adr test pll refclk pllcap dvddio nrst 0.068uf 12mhz in device address l: 33h h: 36h 1.5v dvdd2.8v pllvdd dvss mute_r mute_l dsp cpu 256fs 100uh 0.1uf 220uf 16 audio analyzer 100uh l: reset 20khz lpf a-weight 16 audio analyzer 20khz lpf a-weight vdd_r 2.8v vdd_l 2.8v fig.4 measurement circuit chart recommended parts coil : murata manufacturing lqh32cn101k23 schottky diode : rohm rsx201l-30 capacitor : rohm tctal0g227m8r-d2 technical note 7/15 www.rohm.com 2010.05 - rev.a ? 2010 rohm co., ltd. all rights reserved. BU7839GVW electrical characteristic ta=25degree,dvdd=dvddio=1.5v,vdd_r=vdd_l=pllvdd= 2.8v,refclk=12mhz,fs=44.1khz,f=1khz,load=16 ? , a-weight,20khzlpf,slave mode parameter symbol limits unit condition min typ max static consumption current dvdd idds t - - 10 a at the time of standby static consumption current vdd_r+vdd_l iccst - - 10 a at the time of standby static consumption current pllvdd ip llst - - 10 a at the time of standby consumption current dvdd idd - 0.6 2.0 ma at the time of 0.1mw output (in slave mode) consumption current vdd_r+vdd_l icc - 2. 0 6.0 ma at the time of 0.1mw output consumption current pll ipll - 0.8 2.5 ma output amplitude error vout -2 - 2 db errors with reference to standard values at the time of 0dbfs output are as follows channel-to-channel gain error gerr -1 - 1 db lch-rch s/n sn 60 80 - db 0dbfs, a-weight thd+n thd -40 -60 - db -3dbfs, a-weight channel-to-channel isolation iso 65 80 - db 0dbfs, 1khz bpf psrr psrr - 0 - db technical note 8/15 www.rohm.com 2010.05 - rev.a ? 2010 rohm co., ltd. all rights reserved. BU7839GVW dc characteristic ta=25degree,dvdd=dvddio=1.5v, vdd_r=vdd_l=pllvdd=2.8v item symbol standardized values unit note min typ max input ?h? level vih 0.7x dvddio - - v input ?l? level vil - - 0.3x dvddio v output ?h? level voh 0.8x dvddio - - v io=-1ma output ?l? level 1 vol1 - - 0.2x dvddio v io=1ma output ?l? level 2 (sda terminal) vol2 - - 0.2x dvddio v io=3ma table 10 dc characteristic 2wire cpu i/f part device address is "0110011"(33h) or "0110110"(36h), i.e. 3 3h when adr terminal is l or 36h when adr terminal is h. please don?t switch the adr terminal while 2wire cpu i/f is operating. the transmission rate is compatible with a maximum of 400kbps adr 2wire cpu i/f device address w/r a7 a6 a5 a4 a3 a2 a1 0 0 1 1 0 0 1 1 0/1 1 0 1 1 0 1 1 0 0/1 ? bit transmission the data of 1bit is transmitted while scl is h. in case of bit transmission, the signa l transition of sda can not be implemented while scl is h. if sda changes while scl is h, start condition or stop condit ion is generated, it is interpreted as control signal. sda scl sda stable state: data is effective sda change is possible ? start condition/stop condition data transmission on bus is not implemented while sda and scl are h. at this time, if scl remains to be h and sda is transited from h to l, then the start condition (s) is attained and so the access is started, and if scl remains to be h and sda is transited from l to h, then the stop condition (p ) is attained and so the access is terminated, which is shown below. sda scl s p start condition stop condition this device accepts the continuous start condition and the continuous stop condition. technical note 9/15 www.rohm.com 2010.05 - rev.a ? 2010 rohm co., ltd. all rights reserved. BU7839GVW ? acknowledge after start condition is generated, data is transmitted at 8 bits once. after 8 bit transmission, the transmitter opens sda, and the receiver returns the acknowledge signal with sda taken as l. scl 1 2 8 9 sda output by transmitter sda output by receiver acknowledge non-acknowledge s startcondition clock ulse for acknowledge ? write protocol write protocol is shown below. register address is trans mitted by 1 byte after device address and write command have been transmitted. third byte writes the data, which is written in by second byte, into internal register, and for fourth byte and subsequent bytes, the register addr ess is incremented automatically. but, t he register address becomes 00h by the transmission of 1 byte after the register address has become the final address (6ch). the address is incremented after the transmission is over. s 0 1 1 0 0 1 1 0 a a a7 a6 a5 a4 a3 a2 a1 a0 device address register address r/w=0 (write in) d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 p data data register address increment register address increment a a transmitting set is on master side transmitting set is on slave side a = acknowledge a = non-acknowledge s = start condition p = stop condition sr= retransmission starting condition ? readout protocol readout starts from 1 byte after device address and r/w bi t have been written in. for the address after the readout register is finally accessed and the subsequent addresses, the data of the addresse s that have been incremented is read out. as the readout of 1 byte after the address has become t he final address, 00h is read out. the address is incremented after the transmission is over. s 0 1 1 0 0 1 1 0 a device address data r/w=0 (write in) a d7 d6 d5 d4 d3 d2 d1 d0 data a d7 d6 d5 d4 d3 d2 d1 d0 p register address increment register address increment transmitting set is on master side transmitting set is on slave side a = acknowledge a = non-acknowledge s = start condition p = stop condition sr= retransmission starting condition technical note 10/15 www.rohm.com 2010.05 - rev.a ? 2010 rohm co., ltd. all rights reserved. BU7839GVW ? compound readout protocol after internal address is specified, create the retransmission starting condition, change t he data transmitting direction and implement the readout. subsequently, the data of the address that has been incremented is read ou t. as the readout of 1 byte after the address has become the final address, 00h is read out. the address is incremented after the transmission is over. after retransmission starting condition, compound write is possible with r/w=0 (write in). s 0 1 1 0 0 1 1 0 a a a7 a6 a5 a4 a3 a2 a1 a0 0 1 1 0 0 1 1 1 a sr d7 d6 d5 d4 d3 d2 d1 d0 a d7 d6 d5 d4 d3 d2 d1 d0 a p r/w=0 (white in) r/w=1(read out) device address register address slave address data data register address increment register address increment a = acknowledge a = non-acknowledge s = start condition p = stop condition sr= retransmission starting condition transmitting set is on master side transmitting set is on slave side ? timing diagram scl sda t su;sta t buf t hd;sta t low t high 1/f sclk t su;dat t hd;dat t su;sto (repeated) start condition bit 7 bit 6 acknowledge stop condition ta=25 degree,dvdd=dvddio=1.8v, vdd_r=vdd_l=pllvdd=3.0v item symbol standard mode high-speed mode unit min max min max scl clock frequency f sclk 0 100 0 400 khz hold time of start condition t hd;sta 4.0 - 0.6 - s " " level time of scl t low 4.7 - 1.3 - s "h" level time of scl t high 4.0 - 0.6 - s setup time of repeated start condition t su;sta 4.7 - 0.6 - s data hold time 1 t hd;dat 0.1 3.45 0.1 0.9 s data setup time t su;dat 250 - 100 - ns setup time of stop condition t su;sto 4.0 - 0.6 - s bus opening time between stop condition and start condition t buf 4.7 - 1.3 - s *1 the maximum t hd;dat is not allowed to exceed the ?l? level time t low of scl signal technical note 11/15 www.rohm.com 2010.05 - rev.a ? 2010 rohm co., ltd. all rights reserved. BU7839GVW audio i/f part at slave mode. ta=25degree ,dvdd=dvddio=1.5v, vdd_r=vdd_l=pllvdd=2.8 v parameter symbol limit unit condition min typ max mclk frequency *1 fmclk 2.048 - 18.432 mhz fmclk = 256fs or 384fs mclk duty cycle dmclk 40 - 60 % bclk frequency fbclk 0.512 - 3.072 mhz fbclk = 64fs bclk duty cycle dbclk 40 - 60 % lrclk frequency flrclk 8 - 48 khz flrclk = 1fs lrclk hold time thdlr 80 - - ns sdi setup time tsusdi 80 - - ns sdi hold time thdsdi 80 - - ns *1 it is not necessary to adjust the phase of mclk and bclk and lrclk, but it is ne cessary to be something related to synchroni zation lrclk bclk sdi thdlr fbclk flrclk thdsdi tsusdi thdlr fig.5 audio i/f ac timing(at slave mode) at master mode ta=25degree,dvdd=dvddio=1.5v, vdd_r=vdd_l=pllvdd=2.8v parameter symbol limit unit condition min typ max bclk frequency fbclk 0.512 - 3.072 mhz fbclk = 64fs lrclk frequency flrclk 8 - 48 khz flrclk = 1fs sdi setup time tsusdi 80 - - ns sdi hold time thdsdi 80 - - ns lrclk bclk sdi fbclk flrclk thdsdi tsusdi fig.6 audio i/f ac timing(at master mode) technical note 12/15 www.rohm.com 2010.05 - rev.a ? 2010 rohm co., ltd. all rights reserved. BU7839GVW audio i/f format ?at bit[1:0]=?00? (16bit length) don't care don't care 15 14 13 2 1 0 0 1 2 3 13 14 15 16 17 18 29 30 31 15 14 13 2 1 0 1 2 3 131415161718 293031 0 0 don't care don't care rch lch don't care sdi bclk lrclk don't care 15 14 13 2 1 0 0 1 2 3 13 14 15 16 17 18 29 30 31 15 14 13 2 1 0 1 2 3 131415161718 293031 0 0 don't care don't care don't care 15 rch lch sdi bclk lrclk don't care 15 14 13 2 1 0 0 1 2 3 4 1415161718 19 3031 1 2 3 131415161718 19 3031 0 0 don't care don't care don't care rch lch don't care 15 14 13 2 1 0 sdi bclk lrclk rear stuffing format front stuffing format iisformat ? at bit[1:0]=?01? (18bit length) don't care don't care 17 16 15 2 1 0 0 1 2 3 11 12 13 14 15 16 29 30 31 17 16 15 2 1 0 1 2 3 111213141516 293031 0 0 don't care don't care rch lch don't care sdi bclk lrclk don't care 17 16 15 2 1 0 0 1 2 3 15 16 17 18 19 20 29 30 31 17 16 15 2 1 0 1 2 3 151617181920 293031 0 0 don't care don't care don't care 15 rch lch sdi bclk lrclk don't care 17 16 15 2 1 0 0 1 2 3 4 1617181920 21 3031 1 2 3 131617181920 21 3031 0 0 don't care don't care don't care rch lch don't care 17 16 15 2 1 0 sdi bclk lrclk rear stuffing format front stuffing format iis format technical note 13/15 www.rohm.com 2010.05 - rev.a ? 2010 rohm co., ltd. all rights reserved. BU7839GVW ? at bit[1:0]=?10? (20bit length) don't care don't care 19 18 17 2 1 0 0 1 2 3 10 11 12 13 14 15 29 30 31 19 18 17 2 1 0 1 2 3 131415161718 293031 0 0 don't care don't care rch lch don't care sdi bclk lrclk don't care 19 18 17 2 1 0 0 1 2 3 17 18 19 20 21 22 29 30 31 19 18 17 2 1 0 1 2 3 171819202122 293031 0 0 don't care don't care don't care 19 rch lch sdi bclk lrclk don't care 19 18 17 2 1 0 0 1 2 3 4 1819202122 23 3031 1 2 3 131819202122 23 3031 0 0 don't care don't care don't care rch lch don't care 19 18 17 2 1 0 sdi bclk lrclk front stuffing format iis format rear stuffing format ? at bit[1:0]=?11? (24bit length) 23 24 2 1 0 01 23 5678910 293031 23 22 2 1 0 123 293031 0 0 don't care don't care rch lch don't care sdi bclk lrclk 23 22 21 1 0 0 1 2 3 22 23 24 25 26 27 29 30 31 23 22 21 1 0 123 293031 0 0 don't care don't care 23 rch lch sdi bclk lrclk don't care 23 22 21 1 0 01 2 3 4 3031 123 13 3031 0 0 don't care rch lch don't care 23 22 21 1 0 sdi bclk lrclk rear stuffing format front stuffing format iis format 4 5678910 4 28 22 23 24 25 26 27 28 23 24 25 26 27 2928 23 24 25 26 27 29 28 fig.7 audio i/f format technical note 14/15 www.rohm.com 2010.05 - rev.a ? 2010 rohm co., ltd. all rights reserved. BU7839GVW pll part ta=25degree,dvdd=dvddio=1.5v, vdd_r=vdd_l=pllvdd=2.8v, refclk=12mhz, fs=44.1khz item symbol specification unit condition min typ max lock up time tlock - - 15 msec bclk duty cycle dbclk 40 - 60 % 0.068f mclk refclk pllcap pd 1/n vco 1/m p_pll refclk_enb div_vco n32 n44 n48 m32 m44 m48 1/2 fs 1/4 fs=48k,44.1k,32k fs=24k,22.05k,16k fs=12k,11.025k,8k 1/4 1/256 bclk lrclk slave d-class logic mclk_enb 0 1 slave 12mhz 256fs/384fs 64fs fs fig.8 block diagram of pll part technical note 15/15 www.rohm.com 2010.05 - rev.a ? 2010 rohm co., ltd. all rights reserved. BU7839GVW ordering part number b u 7 8 3 9 g v w - e 2 part no. part no. package gvw:sbga024w040 packaging and forming specification e2: embossed tape and reel ? order quantity needs to be multiple of the minimum quantity. r1010 a www.rohm.com ? 2010 rohm co., ltd. all rights reserved. notice rohm customer support system http://www.rohm.com/contact/ thank you for your accessing to rohm product informations. more detail product informations and catalogs are available, please contact us. notes no copying or reproduction of this document, in part or in whole, is permitted without the consent of rohm co.,ltd. the content specied herein is subject to change for improvement without notice. the content specied herein is for the purpose of introducing rohm's products (hereinafter "products"). if you wish to use any such product, please be sure to refer to the specications, which can be obtained from rohm upon request. examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the information specied in this document. however, should you incur any damage arising from any inaccuracy or misprint of such information, rohm shall bear no responsibility for such damage. the technical information specied herein is intended only to show the typical functions of and examples of application circuits for the products. rohm does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by rohm and other parties. rohm shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. the products specied in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, ofce-automation equipment, commu- nication devices, electronic appliances and amusement devices). the products specied in this document are not designed to be radiation tolerant. while rohm always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the products safety measures to guard against the possibility of physical injury, re or any other damage caused in the event of the failure of any product, such as derating, redunda ncy, re control and fail-safe designs. rohm shall bear no responsibility whatsoever for your use of any product outside of the prescribed scope or not in accordance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospac e machinery, nuclear-reactor controller, fuel- controller or other safety device). rohm shall bear no responsibility in any way for use of any of the products for the above special purposes. if a product is intended to be used for any such special purpose, please contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specied herein that may be controlled under the foreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law. |
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